*********************************************************************
*
* The content of this directory is copyright by Christoph Grimm
* and University of Frankfurt
* It is free for non-commercial use. 
* 
* My adress:
* Christoph Grimm
* J.W. Goethe-University Frankfurt
* Robert-Mayer-Strasse 11-15
* 60054 Frankfurt
* Germany
* 
* Email: 
* grimm@ti.informatik.uni-frankfurt.de
*
*********************************************************************

This directory contains a VHDL-PARSER that allows for example to 
check the syntax of VHDL-files (e. g. for students working
at home at a PC). From version 0.1.0, it also supports the syntax
of the new VHDL-AMS (future IEEE 1076.1). Later versions will
check for compatibility with VI SIWG Level 1 RTL-synthesis-subset.

*********************************************************************
Copyright-Notice:

If you want to use it for other than trial purposes, i need a 
signed agreement of you.  In such a case, send an email to me.
*********************************************************************


HOW TO COMPILE:
===============
jjtree vhdl.jjt (if you have it)
javacc vhdl.jj
javac  *.java
zip vhdlams.zip *.class

Then, edit the script Vhdl to fit your demands. 


HOW TO START:
=============
Vhdl komp.vhd
Vhdl ams.vhd

If it does not work, try:

java Vhdl 

Unfortunately, the JDK for HP seems to be a little bit
buggy. At the moment, i can't compile it on my HP, so
I use a SUN workstation.

Bug reports...
==============
please send comments and bug reports to:

grimm@ti.informatik.uni-frankfurt.de


TODO:
======
During 1. - n.: Remove reported bugs...
Near future:
1. Add VHDL-AMS (IEEE 1076.1) syntax       (OK, in 0.1.0)
2. Add Check for new synthesis - standard  (VI SIWG)  (Coming soon)
3. Add Check for synthesizable subset of SYNOPSYS, MENTOR (???)

Far future:
4. Add symbol tables
5. Dump complete AST+symbol table into a file 
6. Write a small base-class that reads AST 
7. Derive new applications from this small base-class:
    - tool for KANDIS that estimates SYNOPSYS-reports
      (area, delay, ...) from VHDL.


!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!
!!! NO WARRANTY 
!!! for correctness of this grammar
!!! it is still under development 
!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!



